IBM Sets the Course to Build World's First Large-Scale, Fault-Tolerant Quantum Computer at New IBM Quantum Data Center
IBM Sets the Course to Build World's First Large-Scale, Fault-Tolerant Quantum Computer at New IBM Quantum Data Center
IBM unveiled its path to build the world's first large-scale, fault-tolerant quantum computer, setting the stage for practical and scalable quantum computing.
Delivered by 2029, IBM Quantum Starling will be built in a new IBM Quantum Data Center in Poughkeepsie, New York and is expected to perform 20,000 times more operations than today's quantum computers. To represent the computational state of an IBM Starling would require the memory of more than a quindecillion (10^48) of the world's most powerful supercomputers. With Starling, users will be able to fully explore the complexity of its quantum states, which are beyond the limited properties able to be accessed by current quantum computers.
IBM, which already operates a large, global fleet of quantum computers, is releasing a new Quantum Roadmap that outlines its plans to build out a practical, fault-tolerant quantum computer.
'IBM is charting the next frontier in quantum computing,' said Arvind Krishna, Chairman and CEO, IBM. 'Our expertise across mathematics, physics, and engineering is paving the way for a large-scale, fault-tolerant quantum computer — one that will solve real-world challenges and unlock immense possibilities for business.'
A large-scale, fault-tolerant quantum computer with hundreds or thousands of logical qubits could run hundreds of millions to billions of operations, which could accelerate time and cost efficiencies in fields such as drug development, materials discovery, chemistry, and optimization.
Starling will be able to access the computational power required for these problems by running 100 million quantum operations using 200 logical qubits. It will be the foundation for IBM Quantum Blue Jay, which will be capable of executing 1 billion quantum operations over 2,000 logical qubits.
A logical qubit is a unit of an error-corrected quantum computer tasked with storing one qubit's worth of quantum information. It is made from multiple physical qubits working together to store this information and monitor each other for errors.
Like classical computers, quantum computers need to be error corrected to run large workloads without faults. To do so, clusters of physical qubits are used to create a smaller number of logical qubits with lower error rates than the underlying physical qubits. Logical qubit error rates are suppressed exponentially with the size of the cluster, enabling them to run greater numbers of operations.
Creating increasing numbers of logical qubits capable of executing quantum circuits, with as few physical qubits as possible, is critical to quantum computing at scale. Until today, a clear path to building such a fault-tolerant system without unrealistic engineering overhead has not been published.
The Path to Large-Scale Fault Tolerance
The success of executing an efficient fault-tolerant architecture is dependent on the choice of its error-correcting code, and how the system is designed and built to enable this code to scale.
Alternative and previous gold-standard, error-correcting codes present fundamental engineering challenges. To scale, they would require an unfeasible number of physical qubits to create enough logical qubits to perform complex operations – necessitating impractical amounts of infrastructure and control electronics. This renders them unlikely to be able to be implemented beyond small-scale experiments and devices.
A practical, large-scale, fault-tolerant quantum computer requires an architecture that is:
· Fault-tolerant to suppress enough errors for useful algorithms to succeed.
· Able to prepare and measure logical qubits through computation.
· Capable of applying universal instructions to these logical qubits.
· Able to decode measurements from logical qubits in real-time and can alter subsequent instructions.
· Modular to scale to hundreds or thousands of logical qubits to run more complex algorithms.
· Efficient enough to execute meaningful algorithms with realistic physical resources, such as energy and infrastructure.
Today, IBM is introducing two new technical papers that detail how it will solve the above criteria to build a large-scale, fault-tolerant architecture.
The first paper unveils how such a system will process instructions and run operations effectively with qLDPC codes. This work builds on a groundbreaking approach to error correction featured on the cover of Nature that introduced quantum low-density parity check (qLDPC) codes. This code drastically reduces the number of physical qubits needed for error correction and cuts required overhead by approximately 90 percent, compared to other leading codes. Additionally, it lays out the resources required to reliably run large-scale quantum programs to prove the efficiency of such an architecture over others.
The second paper describes how to efficiently decode the information from the physical qubits and charts a path to identify and correct errors in real-time with conventional computing resources.
From Roadmap to Reality
The new IBM Quantum Roadmap outlines the key technology milestones that will demonstrate and execute the criteria for fault tolerance. Each new processor in the roadmap addresses specific challenges to build quantum systems that are modular, scalable, and error-corrected:
· IBM Quantum Loon, expected in 2025, is designed to test architecture components for the qLDPC code, including 'C-couplers' that connect qubits over longer distances within the same chip.
· IBM Quantum Kookaburra, expected in 2026, will be IBM's first modular processor designed to store and process encoded information. It will combine quantum memory with logic operations — the basic building block for scaling fault-tolerant systems beyond a single chip.
· IBM Quantum Cockatoo, expected in 2027, will entangle two Kookaburra modules using 'L-couplers.' This architecture will link quantum chips together like nodes in a larger system, avoiding the need to build impractically large chips.
Together, these advancements are being designed to culminate in Starling in 2029.
To learn more about IBM's path to scaling fault tolerance, read our blog here, and watch our IBM Quantum scientists in this latest video.
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The Path to Large-Scale Fault Tolerance The success of executing an efficient fault-tolerant architecture is dependent on the choice of its error-correcting code, and how the system is designed and built to enable this code to scale. Alternative and previous gold-standard, error-correcting codes present fundamental engineering challenges. To scale, they would require an unfeasible number of physical qubits to create enough logical qubits to perform complex operations – necessitating impractical amounts of infrastructure and control electronics. This renders them unlikely to be able to be implemented beyond small-scale experiments and devices. A practical, large-scale, fault-tolerant quantum computer requires an architecture that is: Fault-tolerant to suppress enough errors for useful algorithms to succeed. to suppress enough errors for useful algorithms to succeed. Able to prepare and measure logical qubits through computation. through computation. Capable of applying universal instructions to these logical qubits. to these logical qubits. Able to decode measurements from logical qubits in real-time and can alter subsequent instructions. and can alter subsequent instructions. Modular to scale to hundreds or thousands of logical qubits to run more complex algorithms. to scale to hundreds or thousands of logical qubits to run more complex algorithms. Efficient enough to execute meaningful algorithms with realistic physical resources, such as energy and infrastructure. Today, IBM is introducing two new technical papers that detail how it will solve the above criteria to build a large-scale, fault-tolerant architecture. The first paper unveils how such a system will process instructions and run operations effectively with qLDPC codes. This work builds on a groundbreaking approach to error correction featured on the cover of Nature that introduced quantum low-density parity check (qLDPC) codes. This code drastically reduces the number of physical qubits needed for error correction and cuts required overhead by approximately 90 percent, compared to other leading codes. Additionally, it lays out the resources required to reliably run large-scale quantum programs to prove the efficiency of such an architecture over others. The second paper describes how to efficiently decode the information from the physical qubits and charts a path to identify and correct errors in real-time with conventional computing resources. From Roadmap to Reality The new IBM Quantum Roadmap outlines the key technology milestones that will demonstrate and execute the criteria for fault tolerance. Each new processor in the roadmap addresses specific challenges to build quantum computers that are modular, scalable, and error-corrected: IBM Quantum Loon , expected in 2025 , is designed to test architecture components for the qLDPC code, including 'C-couplers' that connect qubits over longer distances within the same chip. , expected in , is designed to test architecture components for the qLDPC code, including 'C-couplers' that connect qubits over longer distances within the same chip. IBM Quantum Kookaburra , expected in 2026 , will be IBM's first modular processor designed to store and process encoded information. It will combine quantum memory with logic operations — the basic building block for scaling fault-tolerant systems beyond a single chip. , expected in , will be IBM's first modular processor designed to store and process encoded information. It will combine quantum memory with logic operations — the basic building block for scaling fault-tolerant systems beyond a single chip. IBM Quantum Cockatoo, expected in 2027, will entangle two Kookaburra modules using 'L-couplers.' This architecture will link quantum chips together like nodes in a larger system, avoiding the need to build impractically large chips. Together, these advancements are being designed to culminate in Starling in 2029.
